XMCV5 is the first rugged XMC to harness the power and flexibility of all three Virtex-5 FPGA families with build options for the Virtex-5 FX100T, SX95T and Virtex-5 LX110T enabling customers to field the right solution and address the complete range of performance requirements for demanding defense and aerospace applications.
XMCV5 is designed for a wide spectrum of digital signal processing (DSP) applications in ground mobile, airborne fixed- and rotary wing and naval applications including radar, sonar, signal intelligence (SIGINT), and image processing. It can be hosted on a broad range of Abaco Systems' 3U and 6U single board computers (SBCs), including the VMEbus PPC9A and VPX SBCs such as SBC610 and SBC310. Compliant with the VITA-42 XMC mezzanine card base standard, XMCV5 is available in both VITA 42.3 (PCIe) and VITA 42.2 (Serial RapidIO) configurations.
Together with our latest PowerPC and INTEL architecture processors, XMCV5 offers the right balance between hardware oriented FPGA optimized computing and software based application code running on the host platform. Abaco Systems offers the widest range of innovative COTS solutions from rugged single board computers, carrier cards, multiprocessors to sensor I/O and complete system solutions.
VWRAP support is delivered in the form of an ISE or EDK project with a variety of tested cores to support baseline connectivity providing a quick start reference for application development using the standard Xilinx tool chain. Our multiprocessor support includes Abaco Systems' AXIS Advanced Multiprocessor Integrated Software suite of fully integrated modules for system development, visualization and deployment running on the host CPU with support for a range of system fabrics: GbE, sRIO and PCIe.
- Xilinx Virtex-5 FPGA: FX100T with PPC440 hard cores, SX95T or LX110T
- External Memory: QDR2 SRAM, DDR2 SDRAM and SPI Flash
- Rear I/O
- VITA 42.3 PCIe gen2 (to 5 GHz) or VITA 42.2 sRIO build option
- Rocket I/O to 6.5 GHz via GTX ports
- LVDS, GPIO, GbE, Serial ports
- Front I/O: GbE, Serial, LVDS, GPIO
- EDK and ISE project with tested cores
- Quick start FPGA image
- Ruggedization Levels
- XMCV5 Press Release
Article - Advances in Radar Processing (Military & Aerospace Electronics July 2008)