FMC422 FPGA Mezzanine Card

Dual Camera Link FMC

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Overview

The FMC422 is a dual base or single/medium/full Camera Link FPGA Mezzanine Card (FMC) for advanced video processing applications requiring high performance capture or output and FPGA processing.

The FMC422 provides the optimum solution for new systems as well as a straightforward technology refresh/performance upgrade for existing systems. When paired with one of Abaco’s state of the art FPGA carriers, the FMC422 makes it easy to perform the most advanced real-time video processing applications. Applications include low latency video sensors for degraded visual environment navigation, autonomous vehicles, and defense active protection systems.

A direct LVDS connection to the FPGA enables you to leverage modern FPGAs and potentially run at a faster data rate than the standard defines.

The FMC422 is fully VITA 57.1 compliant and only requires an FPGA carrier with the low pin count (LPC) configuration, making it possible to mount on both HPC and LPC FPGA carriers. The FMC422 includes a version 2 compliant Power over Camera Link (PoCL) interface, passing power over pins 1 and 26.

Specifications

Form Factor

FMC

Cooling

Air, Conduction

Function

CameraLink Video Interface

Data Rate

255MB/s (Base), 510MB/s (Medium), 680MB/s (Full)

Channels

Resolution

24-bit (Base), 48-bit (Medium), 64-bit (Full)

FMC Connector

HPC

Downloads

Datasheets

Manuals

FMC422 User Manual

Brochures

White Papers

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Dual Camera Link FMC

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Dual Camera Link FMC

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Dual Camera Link FMC

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FMC

Addressing the challenges of low latency video system requirements for embedded applications

Here, Larry Schaffer, Director of Business Development and Haydn Nelson, Director of Product Management, RF and DSP review the sources of latency, and how to minimize it.

DOWNLOAD WHITE PAPER ALL WHITE PAPERS

FPGA DSP Board Support Package

Our FPGA DSP Board Support Package gives you complete control, flexibility and power to develop solutions for the most demanding DSP applications. It's built upon pre-validated IP blocks that have been designed to minimize FPGA resource utilization - giving you as much programmable logic for your application as possible.

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