Abaco Systems P/N 7079 addresses a need for a 16 bit digital I/O ECM with +5V high drive logic levels and configurable grounding. (An alternate population of the interface chips allows +3.3V logic levels.) Designed around an Altera 128 logic cell CPLD for I/O control, The default CPLD design allows for byte wide configuration of the I/Os and implements a secondary serial ID. Configuration changes to the CPLD can be easily programmed via JTAG pins driven by the FPGA. The I/Os are driven by tri-stateable 74ABT126 drivers and also routed to an input pin on the CPLD, allowing use as inputs, outputs or outputs with a sense input on a byte-wide basis in the default design. On power up the I/Os are set as inputs pending configuration. In the standard design, each I/O bit is connected to a driver by a zero ohm series resistor. Alternatively, I/O can tied to a hard ground on the connector. This permits configuration of alternating signal-ground-signal-ground pin outs on the I/O connector. The digital outputs provide high drive (−32mA IOH, 64mA IOL) and enter a high-impedance state during power up and power down. For more details about refer to the 74ABT126 datasheet.