Accelerate multi-channel synchronization development.
Many EW, SIGINT and MIMO applications begin with channel-to-channel synchronization; however, that one step can take months to achieve. The SRS6000 and its in-built auto-calibration algorithm make this a task of minutes - not months. In addition, should your cabling or setup change, the calibration routine will automatically adjust.
With powerful processing capabilities and out-of the-box synchronization of 32 1GSPS ADC channels with picosecond jitter, and the ability to daisy chain up to eight systems for a total of 256 synchronized channels, the SRS6000 provides a new degree of precision, performance and extensibility for MIMO, beamforming, and radar processing applications.
Scalable and extensible.
Other hardware configurations are possible with limited development, making the SRS6000 an ideal starting point for other application requirements.
While the out-of-the box SRS6000 is a PCIe™ based system, there is a simple migration path to a 3U VPX solution with minimal development work required.
With two Intel® 2.2GHz Xeon® E5 processors and five Xilinx® Ultrascale™ FPGAs, the SRS6000 provides server grade processing for the most computationally intensive applications. Additionally, PCIe Gen3x8 and FireFly™ x8 fiber optic interconnects provide extreme throughput for powerful streaming.
- A guide to multi-channel synchronization for MIMO systems
- Addressing the challenges of low latency video system requirements for embedded applications
- Electronic warfare: an introduction to low latency COTS solutions
- Hypersonic Flight Raises the Bar for Embedded Electronics
- Leveraging FPGAs for Evolving ISR Application Requirements.
- RFSoC for Radar and Electronic Warfare
- Selecting the Optimal DSP Solution for EW Applications
- Technologies for responding to rapid developments in cognitive RF and EW
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FPGA DSP Board Support Package
Our FPGA DSP Board Support Package gives you complete control, flexibility and power to develop solutions for the most demanding DSP applications. It's built upon pre-validated IP blocks that have been designed to minimize FPGA resource utilization - giving you as much programmable logic for your application as possible.