We recommend the following alternative solutions:
Abaco Systems' Serial Front Panel Data Port (sFPDP) IP core for FPGAs is based on the ANSI/VITA 17.1-2003 standard. The 4DSP sFPDP IP core is a serial communication protocol designed to provide low latency and high transfer rates. Real-time applications benefit from the high performance and low overhead built into the core. This intellectual property core can be implemented on any Xilinx FPGA family and is rated for transfer speeds of up to 5Gbps data rates. The use of fiber optic cables allows sFPDP to operate over long distances (up to 10KM).
The heart of the sFPFP core lies within the sFPDP transceiver module which takes care of encoding and decoding the sFPDP packets. The sFPDP protocol allows connectivity directly to the transmit input and output of a Xilinx MGT or GTP.
This protocol is available pre-ported to a number of PMC - XMC boards as a turnkey, plug-n-play solution for any PMC - XMC host motherboard. 4DSP’s intuitive StellarIP FPGA development tool is available for this product. It offers a simple way to design FPGA firmware with automated code and bitstream generation.
- Up to 5Gbps (using MGTs)
- Up to 230MBytes/s per optical transceiver for 2.5 Gbps, 460MBytes/s for 5Gbps
- Unidirectional and bi-directional links
- Framing supported: dataflow control, PIO per specification, copy mode, copy-loop mode and CRC
- Fully compliant ANSI/VITA 17.1-2003 SFPDP standard
- Virtex UltraScale
- Kintex UltraScale
Abaco Target Boards
- FM780 (Virtex-7 XC7VX485T, XC7VX980T, XC7VX690T, XC7VX1140T)
- VP780 (Virtex-7 XC7VX485T, XC7VX690T, XC7VX980T, XC7VX1140T)
- PC720 (Kintex-7 160T, 325T, 410T)
- PC820 (Virtex UltraScale XCVU080, XCVU095, XCVU125 or Kintex UltraScale XCKU085, XCKU095, XCKU115)
- PC821 (Virtex UltraScale XCVU080, XCVU095, XCVU125 or Kintex UltraScale XCKU085, XCKU095, XCKU115)
- A guide to multi-channel synchronization for MIMO systems
- Addressing the challenges of low latency video system requirements for embedded applications
- Creating Flexible Hardware Systems with FPGA Partial Reconfiguration
- Electronic warfare: an introduction to low latency COTS solutions
- Leveraging FPGAs for Evolving ISR Application Requirements.
- Selecting the Optimal DSP Solution for EW Applications
- Technologies for responding to rapid developments in cognitive RF and EW