The FMC667 is a Digital Signal Processor FMC daughter card based on the Texas Instruments TMS320C6678 device. The FMC667 daughter card is mechanically and electrically compliant with the FMC standard (ANSI/VITA 57.1), and can be used in a conduction cooled environment.
This FMC is equipped with power supply and temperature monitoring and offers several power-down modes to switch off unused functions and peripheral interfaces. Several Gigabit differential pairs from the FMC connector are used to implement a PCIe and Serial Rapid IO interface between the FMC and the carrier. Many other digital I/O interfaces are also made available to the FMC carrier.
Because of the use of level translators between the DSP and the FMC connector the FMC667 can fully operate on any VITA 57.1 compliant carrier. A 1GB DDR3 SDRAM on-board bank directly connects to the DSP thus providing the FMC667 with the memory resources required for demanding signal processing applications.
The TMS320C6678 Multicore Fixed and Floating Point Digital Signal Processor is based on TI’s KeyStone multicore architecture. Integrated with eight C66x CorePac DSPs, each core runs at 1.0 to 1.25 GHz enabling up to 10 GHz.
The device supports high-performance signal processing applications such as mission critical signal processing, medical imaging, test, and automation.
- A guide to multi-channel synchronization for MIMO systems
- Addressing the challenges of low latency video system requirements for embedded applications
- Electronic warfare: an introduction to low latency COTS solutions
- Hypersonic Flight Raises the Bar for Embedded Electronics
- Leveraging FPGAs for Evolving ISR Application Requirements.
- RFSoC for Radar and Electronic Warfare
- Selecting the Optimal DSP Solution for EW Applications
- Technologies for responding to rapid developments in cognitive RF and EW
Request a Quote
Contact an Expert
FPGA DSP Board Support Package
Our FPGA DSP Board Support Package gives you complete control, flexibility and power to develop solutions for the most demanding DSP applications. It's built upon pre-validated IP blocks that have been designed to minimize FPGA resource utilization - giving you as much programmable logic for your application as possible.