This Application Note provides the basic information required to implement a True Dual-Port interface between the host and the CORE. The standard host interface to the CORE restricts the host access rate to, not greater than, one access every 500nsec. In some cases, a higher access rate is required. This can be achieved by taking advantage of the True Dual-Port memory that is available in most FPGAs today. This Application Note assumes that the physical Dual-Port memory is located internal to the FGPA. It also assumes a basic knowledge of memory interfaces and Verilog HDL.