AUSA’s Annual Meeting and Exposition is described as the largest land power trade show in North America. The Association of the United States Army is a non-profit educational and professional development association serving America’s Army and supporters of a strong national defense.
Abaco sonar solutions are deployed on countless vessels around the world, including the US Navy’s Virginia Class submarine.
Abaco Systems was one of the first companies to offer commercial off-the-shelf (COTS) products for acoustic applications, and today we offer an extensive range of solutions. Our products span the popular embedded computing architectures, including OpenVPX, VME and CompactPCI, and offer the powerful features that are key to acoustic applications.
We have been delivering state-of-the-art military computing sonar solutions for more than 30 years, so it’s not surprising that the industry’s leading prime contractors choose our products in many of their highest profile programs. In addition to our invaluable experience in sonar, our field-proven hardware offerings reach all the way from front-end data acquisition to back-end signal processing.
Our software toolset, AXIS (Advanced Multiprocessor Integrated Software), enables rapid, efficient development, debugging and deployment of sophisticated, high-performance signal processing applications. It is this expertise, hardware, software that sets Abaco Systems apart.
Abaco Systems is a leader in combining high performance with the rugged reliability required for operation in hostile environments - all the while, maintaining minimum size, weight and power (SWaP) to enable deployment in the broadest possible range of environments.
Front end processing
For sonar applications, the two main considerations are the signal-to-noise ratio and the phase matching of the analog-to-digital conversion process.
Maximizing the signal-to-noise ratio is increasingly important to sonar designers because of threats with low signature responses such as the latest diesel generators. Once a signal is successfully received, it is impossible to locate the source without accurate phase information.
Minimize to maximize
The skill in designing for signal-to-noise ratio is to minimize the noise to maximize the signal itself. Minimizing noise will typically mean ensuring that the ADC silicon is separated from the digital components on the board. It should have its own filtered power supply, and other components should be placed on the board so that interference is minimized. Fully differential circuits should be used wherever possible.
Maximizing signal quality will typically require signal conditioning – ideally, on the data acquisition board itself. Signal conditioning can include functions such as signal amplification, attenuation, filtering and electrical isolation.
Detecting a signal may be important, but it is of little use unless the location can be determined. Careful phase matching across all channels on a circuit card, and all channels across multiple synchronized circuit cards, has been our design goal since day one. This applies not only to the start of acquisition, but also to ensuring that phase information is maintained during continuous operation.
Our products offer three levels of redundant synchronization designed solely to maintain this important information.
Back end processing
Once the data have been acquired, the next hurdle is equally daunting: designing and debugging the complex back-end processing system across multiple processing nodes. Abaco Systems offers a leading combination of hardware and software designed not only to deliver state-of-the-art performance as rapidly as possible, but to support the deployment of that performance. Our AXIS applications development toolset is specifically designed to simplify the development of complex signal processing applications requiring Intel or GPGPU-based multiprocessor systems.
Abaco also offers the specialized types of hardware required for these demanding applications. For example, the DSP282A features two Quad Core i7 multiprocessors offering 665.6 GFLOPS per card slot of peak performance, coupled with 40 Gigabit Ethernet switching on the data plane. Its high-performance embedded computing (HPEC) architecture can scale from one to many processor nodes per 6U VPX enclosure with inter-node communication over PCIe™ gen 3 and OFED RDMA or Ethernet data plane via the latest Mellanox ConnectX™ -3 network interface controller (rNICs), delivering up to 1.8 GBytes/second data rates per channel with memory to memory latencies of approximately 1µs..
Massively parallel processing
For applications requiring the massively parallel characteristics of GPU technology, we offer the NPN240 with dual NVIDIA GT240 96-core GPUs, delivering up to 750 GigaFLOPS peak per card slot (depending on the application).
Multiple NPN240s can be linked to single or multiple hosts to create multi-node CUDA GPU clusters capable of thousands of GFLOPs. Providing a highly computationally-dense platform, the NPN240 is ideal for demanding applications that are constrained in terms of size, weight and power.
Combining CPU with GPU
For the best of both worlds, we also offer the IPN252 which combines NVIDIA's latest GM107 640-core GPU with an Intel® Core™ i7 processor operating at 2.1 GHz and up to 16 GBytes of DDR3 SDRAM, delivering up to 1.4 TeraFLOPS of performance per card slot, depending on the application.
It is designed from the ground up to be compliant with the OpenVPX standard, ensuring interoperability with a broad range of other OpenVPX boards. It is VITA48/REDI-compliant, allowing it to be deployed in the harshest of environments; build options for air- spray- and conduction cooling are available.