FMC121 FPGA Mezzanine Card

Analog input and output

FMC121
FMC121 

This product is no longer recommended for new designs.

Product Details

The FMC121 provides two 16-bit A/D channels up to 1 GSPS and two 16-bit D/A channels up to 1.4 GSPS data rate with a 2.8 GSPS update rate.

 

The design is based on Texas Instruments' ADS54J60 Analog-to-Digital converter and Texas Instruments' DAC39J84 Digital-to-Analog converter.

 

The sample clock can be supplied externally through a coaxial connection or supplied by an internal clock source (optionally locked to an external reference) for multi-channel synchronization. An external trigger input is available for timing synchronization.

 

The FMC121 is mechanically and electrically compliant with the FMC standard (ANSI/VITA 57.1). The card connects to an FPGA carrier card through a standard high-pin count (HPC) connector.

 

Front panel I/O can optionally be populated with MMCX or SSMC coaxial connectors. Analog I/O is DC coupled.

The FMC121 is designed to be used in convection or conduction cooled environments. When paired with the latest FPGA carrier cards such as the Abaco Systems PC821 with Xilinx Ultrascale technology, customers can develop innovative high performance algorithms on an industry standard platform.

Board Support Package

Our Board Support Package helps customers get their hardware implementation underway as quickly as possible by providing reference designs, the Stellar IP FPGA development tool, and the 4FM GUI user interface for controlling and monitoring the hardware, as well as other supporting elements.

Downloads

Brochure

Abaco Systems Product Selection Guide

PDF

Advanced RF and DSP Solutions

PDF

Case Studies

Advanced Radio Astronomy Systems for Universal Observations

PDF

Datasheet

FMC121 Datasheet

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FPGA Board Support Package

PDF

Ruggedization Levels Datasheet

PDF

Solution Briefs

RFSoC for Radar and Electronic Warfare

PDF

Electronic warfare sensor processing in a SWaP-constrained

PDF

White Paper

A guide to multi-channel synchronization for MIMO systems

PDF

A guide to multi-channel synchronization for MIMO systems

PDF

Addressing the challenges of low latency for embedded applications

PDF

Creating Flexible Hardware Systems with FPGA Partial Reconfiguration

PDF

Electronic warfare: an introduction to low latency COTS solutions

PDF

Hypersonic Flight Raises the Bar for Embedded Electronics

PDF

Leveraging FPGAs for Evolving ISR Application Requirements.

PDF

Selecting the Optimal DSP Solution for EW Applications

PDF

Technologies for responding to in cognitive RF and EW

PDF

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Analog input and output