FPGAs for Electronic Warfare: What a Difference in 10 Years
The evolution of programmable logic devices over the past twenty years has been very interesting to be a part of. They have evolved from simple, one-time programmable devices used mostly as interface glue to being a central component in the most advanced signal processing systems.
My passion for FPGA capability and technology has been a constant throughout my career. I specialized in digital embedded systems at the University of Texas and was fortunate enough to get a job working with FPGAs and RF immediately after graduation. Ten years ago, I worked with some of the smartest engineers in industry and we developed what I believe was one of the most advanced DRFMs at the time using FPGAs. The system used the first generation Altera Stratix FPGA and a single ADC and DAC running at 100MSPS—and it was awesome!
The ADC was state-of-the-art and we couldn’t even buy it yet. We were forced to use engineering samples. From the analog design to the DSP algorithm development, the project took about a year and a half. Unfortunately, there wasn’t the concept of FPGA-based COTS yet. If I could have purchased that PCB rather than build it, I could have saved a lot of time and reduced the project cost. The silver lining was that, by building the system ourselves, we learned a lot since there were many bugs and design errors ranging from noisy ground planes to software/firmware glitches. With good engineering practices, the result was a very capable system that led to advancing state-of-the-art technology for EW and ultimately to saving lives on the battlefield when used operationally.
Typical EW/DRFM System Components
It’s interesting to compare the system I helped build ten years ago to EW platforms today. Back then, firmware designs were much simpler, since both the ADC/DAC and FPGA were running at 100MHz. Today, ADCs and DACs run higher than 5GSPS and FPGAs clock around 500MHz. The FPGA logic resources-per-sample has increased dramatically. Additionally, single channel systems are no longer the norm. Today, with digital beam forming, MIMO, and other advanced techniques it’s not uncommon to require 16, 32, or more channels in an EW system. More channels combined with faster data has substantially increased the need for more FPGA processing logic elements over the years.
Fortunately, our friends at Altera and Xilinx have delivered on the promise of Moore’s Law as applied to FPGAs with increasingly more and more general purpose resources. Since FPGAs have become prolific in DSP applications, many FPGAs include specialized blocks for DSP processing functionality. In our design 10 years ago, we used a VHDL-based soft embedded processor from Altera called the NIOS. They still offer this today and it is useful in many applications. Xilinx offers a similar capability called a Microblaze.
While the soft embedded processor is very useful, it can take a lot of valuable FPGA logic resources and will never match the performance of a built-in silicon processor design. Thus, over the past five years, we’ve seen the introduction of system-on-chip devices such as the Xilinx Zynq series. On the horizon today is the Zynq Ultrascale+ which should release to full production soon and is considered a multi-processor system-on-chip (MPSOC). Altera has similar MPSOC designs with their coming Stratix 10-based devices. This combination of embedded processor mapped directly to an FPGA fabric is an enabling technology for applications—especially in the military embedded space, as it provides both reconfigurable logic and general purpose processing. However, the pure reconfigurable logic fabric-only devices still have their place.
We’ve seen the evolution in the Virtex/Kintex series of devices from 1 to 7—and now Ultrascale and beyond. Just looking at the processing resources from Virtex 7 to Ultrascale class devices, we’ve roughly doubled in resources while halving in power consumption. Going forward, the next generation of Ultrascale+ is further pushing what is possible with FPGAs as a DSP processing technology.
Since FPGA card designs are getting increasingly more complex—having a complete processor, FPGA, and I/O all on a single board—it’s becoming riskier and cost-prohibitive to design such a board from scratch. An additional challenge is keeping pace with evolving technology. COTS hardware providers like Abaco can help. At Abaco we have a close relationship with chip manufacturers like Xilinx, which helps us gain early access to FPGA devices and build a single board that can support multiple devices. This allows us to better support our customers by making it easier to keep pace with the latest technology or even just scale an existing design to more resources by changing a single chip.
The recent release of the VP880 is a great example. It incorporates the Zynq Ultrascale+, the latest MPSoC, as well as the Virtex or Kintex Ultrascale FPGA devices. The VP880 was designed with upgradability in mind. It is already compatible with some Ultrascale+ FPGAs that are set to be released later in 2017. While no technology is 100% obsolescence proof, the VP880 is as close as you will get.
Technology for EW systems has come a long way. The system I built ten years ago seems primitive when compared to products like the VP880, FPGAs, I/O and their part in high performance digital systems. What will the next devices include? Time will tell. However, it’s clear that no single processing architecture tool is perfect for all jobs—but having the modular technology to apply the right tool in a fast and affordable way will be key to meeting the demands of next generation EW systems.