Having worked with various silicon processing technologies for well over 14 years, I’ve witnessed how Moore’s Law has impacted CPU, GPU, and FPGA devices. Back in 2004, I was a part of a research group under Annant Agarwal at MIT CSAIL where students prototyped a 16-core processor. This was a project called the MIT RAW architecture workstation and was a tiled design. At that time, such a massive multi-core system was revolutionary. Since then, Moore’s Law has marched on and now we have GPU chips with thousands of cores.
As more real estate is available it’s always a question of what do you do with it?
Traditional CPUs consumed silicon resources with ever more complex micro-architectures that required many complex and creative innovations such as out-of-order-execution, multi-level caching, and adaptive branch prediction. Many of these uses of silicon were pioneered by the HPS group at University of Texas at Austin under Professor Yale Patt. At some point, as CPUs grew bigger and clock rate scaling became an issue, then it was harder to take advantage of the added silicon; thus we saw the introduction of multi-core processors for these advanced architectures such as x86. Multi-core is now ubiquitous from all CPU suppliers.
On the FPGA side, the growth in silicon has seen similar multi-function integration. I believe, as excess silicon was available, the FPGA was a natural evolution of the CPLD, as the FPGA enabled IP debugging in circuit and prototyping. Today, FPGAs are a mainstay for digital signal processing and adaptive computing as they are inherently reprogrammable. As far as functional blocks are concerned, early FPGAs were a collection of logical look-up tables connected together with routing fabrics. The term “Fabric FPGA” is often used for this core functionality and we’ve seen massive growth in the resources included in these devices over the years.
Even with the power of a purely reconfigurable fabric, many designers found the benefit of ‘hardened’ core functions attractive. Early designs included Block RAM and DSP functions. There is no denying that certain computational problems are better suited for a sequential CPU that can be programmed easily with languages like C/C++. From this need we’ve seen the innovation of integrated CPUs and FPGAs as a ‘system-on-chip’ (SoC). Xilinx calls this capability an MPSoC and brands its multi-processor system-on-chip “Zynq”.
In 2017, Abaco released the VP880 and VP881 series 3U VPX FPGA Carriers that included the ability to use both Kintex and Virtex Ultrascale class devices. These boards not only included the traditional fabric style FPGA, but also included the Zynq architecture with the all new Zynq Ultrascale+. This new ZU+ device has many security and peripheral interface features built in.
Expanded product line
Moore’s Law has continued to march on, and Xilinx recently released its Ultrascale+ class devices which are a die shrink that improves computational resources, as well as improving power consumption performance. At Abaco, we’ve truly sought to stay at the leading edge of FPGA technology, and we recently expanded our VP88x product line with the VP889 which now includes the Virtex Ultrascale+ VU5P and VU9P class devices. This is in keeping with our commitment to our customers and the EW industry to deliver on the promise of Moore’s Law and cutting edge technology in COTS standard form factors.
As Moore’s Law marches on, we see the integration of RF on the horizon with the Xilinx RFSoC and it will be interesting to see how the inexorable progress that Moore foresaw will drive more capabilities and more functionality; truly propel technology miniaturization; and realize the vision of an adaptive intelligent world based on this cutting edge technology.