In the first part of this blog post, I outlined the growing necessity for our armed forces to “own” the electromagnetic spectrum – and the challenges faced in delivering the technology that can enable that to happen. In part two, I look at a new product – the VP430 - that we announced yesterday and that has significant potential to rise to those challenges.
The Zynq UltraScale+ RFSoC devices - a new innovation from Xilinx – can, we believe, help us provide a solution for wider bandwidth, more channels and high adaptability, with the potential for even greater flexibility if it can be pushed closer to the antenna.
This family of devices features an integrated ADC (up to 16 12-bit channels sampling at 4.0 GSPS), DAC (up to 16 14-bit channels sampling at 6.4GSPS), configurable logic elements, multi-processor embedded ARM Cortex-A53 application processing unit (APU), and an ARM real time processing unit (RPU). Integrating all of these devices enables the shifting of many of the analog signal processing actions - that typically take place close to the antenna in a digital receiver - into the digital domain. Doing so helps reduce the RF signal processing chain complexity, standardize on one set of flexible hardware to address a variety of applications, maximize input/output channel density without sacrificing wide bandwidth and leverage heterogeneous processing capabilities – all of this while taking advantage of the Zynq architecture’s built-in security features that help keep IP safe.
Reducing RF Signal Chain Complexity
Radar and EW systems with multiple channels suffer from a cost and complexity challenge, in that more channels means more expensive and large RF signal up/down conversion and signal conditioning. A common solution to this is direct RF sampling – a more flexible approach than traditional analog frequency translation and filtering. Direct RF sampling can be implemented in the digital domain, which draws less power and generally costs less.
This means that the RF frond end can handle wider bandwidths than traditional analog technologies while consuming less power. Using very high sample rates in the data converter, as the RFSoC devices do, means that much of the analog filtering and conditioning can be done closer to the antenna, providing a simpler, more flexible front end than has been possible in the past.
Introducing the VP430
The VP430 Direct RF Processing System, with an 8-channel ADC and 8-channel DAC, provides this benefit and helps minimize the need for complex up conversion and down conversion for many frequency ranges common in radar, communications, and electronic warfare. For radar and EW systems, this means there is more control over the digital signal processing at the software level so that the overall system can be adapted more rapidly as new threats emerge. This also lays the groundwork for truly cognitive radar and EW.
Additionally, since ADCs and DACs were historically separate devices from the programmable FPGA, a high speed interface was needed to communicate between the devices. In recent years, JESD204B has been a common high speed serial interface – but it comes at a cost in terms of latency and design complexity. For some radar or EW applications, the latency from JESD204B is too large, often ruling devices that use this interface out for system integration. The RFSoC helps overcome this. By integrating the ADCs and DACs into the device, the need for JESD204B is eliminated – simplifying design complexity and helping reduce latency.
This is particularly applicable for the growing demand for cognitive or smart radar/EW technology. Additionally, simplified integration with RF sampling devices removes the complexity of JESD204B high speed serial interfaces. This means that fewer programmable logic elements are consumed by basic functions like inter-device communication, leaving more computational resources available to application-specific IP than in the past.
In addition to gaining all the above-mentioned benefits of the RFSoC device, the VP430 can also help offload data more efficiently by taking advantage of an optional 8-channel VITA 66.4 fiber optic interface.
Firehose of data
When a system includes many channels and extreme sample rates, there is always the problem of how to handle the firehose of data. Invariably, a system must decimate, process, or transfer the data in the FPGA. Many times, a system is limited to the data connection fabric. The VP430 has a traditional VPX data plane interface, allowing a x8 PCIe Gen3 connection to a host computer. With eight ADCs sampling at rates over 6GSPS with two bytes per sample, even the modern PCIe Gen 3 high speed data connection is too slow for a direct transfer. To overcome this challenge, the VP430 includes – in addition to the PCIe Gen3 data plane - the option to be built with an 8-channel VITA 66.4 fiber optic interface for transfers of greater than 12 GBPS per channel.
Controlling the electromagnetic spectrum on the battlefield is essential to mission success. A major factor in capturing and maintaining that control is having the most advanced radar and electronic warfare systems. Future systems must be powerful enough to monitor and manipulate wide bandwidths while also being flexible enough to adapt in as close to real time as possible. Leveraging technologies like the RFSoC can help give the armed forces the edge they need to be more adaptable than their adversaries.
The image above is a work of a sailor or employee of the U.S. Navy, taken or made as part of that person's official duties. As a work of the U.S. federal government, the image is in the public domain in the United States.